AMD EPYC 9645 socket: SP5

What the EPYC 9645 is

The EPYC 9645 is a 96-core, 192-thread dense server processor that AMD released on October 10, 2024 with Turin. Zen 5c compact cores on TSMC 3 nm run at 2.3 GHz base with boost to 3.7 GHz and all-core boost at 3.3 GHz. Shared L3 cache totals 256 MB. Default TDP is 320 W configurable between 320 and 400 W.

A note on sources: one press table printed 384 MB of cache for this SKU, but the AMD product page and datasheet agree on 256 MB, which this page follows for this efficient dense configuration. Against the 96-core classic AMD EPYC 9655 at 400 W the 9645 trades clocks and cache for lower power with the same thread count. Dense dies carry 16 cores each, so six dies cover the socket with room for straightforward NUMA grouping and growth.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. The 320 W default is the lowest power in the 96-core class, which suits racks provisioned under the 400 W flagships with margin for peaks.

Workload fit is efficient density: clouds that want 192 threads per socket inside 320 W racks, plus container platforms scaling by thread count with strict power caps. Operators pick the 9645 where the 9655 exceeds power budgets but 72 dense cores fall short on threads for growing platforms and tenants.

Socket and motherboard compatibility

The 9645 fits the SP5 socket in FC-LGA6096 packaging on boards covering the 320 to 400 W band. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS.

One or two sockets are supported. Dual-socket pairs deliver 192 cores with 24 memory channels for large scale-out tenants with headroom for growth, while single-socket use contains per-socket licensing for predictable renewals. Memory per thread stays thin, so capacity planning decides tenant sizes before core counts do for dense duty at scale.

Boards carried over from Genoa need Turin stepping confirmation per revision. Mixed dense and classic fleets share firmware trains, spares and management tooling across both core types for simpler operations.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 96 dense cores the memory per thread needs high-capacity DIMMs to keep tenants comfortable during peak concurrency and batch windows every day. Fully populated channels with matched parts keep bandwidth uniform. The board memory guide sets legal mixes for the configurable envelope.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across one or two CPUs. Dense hosts attach many endpoints per socket, and lane planning should reserve paths for every device from the start.

Cooling at 320 W uses vendor-qualified high-performance air or liquid heatsinks matched to chassis height. No tray cooler ships. The 320 W default eases qualification against 400 W siblings while keeping all 192 threads for dense duty.

Upgrade paths

Inside SP5 the 9645 grows from smaller dense SKUs for threads or trims from the 96-core classic AMD EPYC 9655 for power, reusing boards and memory with a BIOS check. Each move needs matching cooling for the envelope. Tenant density targets deserve revalidation after any swap between density classes with different cache ratios and clock bands.

Larger dense options such as the AMD EPYC 9965 add threads at higher power on the same platform for hyperscale tenants with room to grow. Leaving SP5 entirely waits for later sockets with fresh memory qualification for efficient dense refreshes.