AMD EPYC 9755 socket: SP5

What the EPYC 9755 is

The EPYC 9755 is a 128-core, 256-thread server processor that AMD released on October 10, 2024 as the densest Zen 5 classic SKU of Turin. Cores run at 2.7 GHz base with boost to 4.1 GHz and all-core boost at 4.1 GHz. Shared L3 cache totals 512 MB across sixteen compute dies. Default TDP is 500 W configurable between 450 and 500 W.

It is the full-size counterpart to the 128-core Zen 5c AMD EPYC 9745: same thread count with double the cache (512 MB against 256 MB) and higher clocks at higher power, since classic Zen 5 dies carry 8 cores with 32 MB each. Against the 96-core AMD EPYC 9655 it adds 32 cores for maximum consolidation per socket. The embedded twin AMD EPYC Embedded 9755 serves industrial carriers.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. With 256 threads per socket, cloud hosts pack the most guests per rack unit in the classic-core line. Power capping down to 450 W fits constrained feeds with a small clock cost.

Workload fit is maximum consolidation: service providers that rent virtual machines by the dozen per host, private clouds collapsing racks, and HPC centers running throughput ensembles. Operators compare the 9755 against the dense-core AMD EPYC 9965 for thread-first hosting, since 192 Zen 5c cores beat 128 classic cores where per-thread speed matters least.

Socket and motherboard compatibility

The 9755 fits the SP5 socket in FC-LGA6096 packaging on dual-capable boards with 500 W delivery. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and voltage regulation plus retention assume the full envelope.

One or two sockets are supported. Dual-socket 9755 pairs deliver 256 cores with 24 memory channels for the largest guests, while single-socket use keeps per-socket licensing contained. Memory per core runs thinner here than on smaller SKUs, so capacity planning decides consolidation ratios.

Boards need robust power stages with heatsinked delivery for sustained 500 W operation. Confirm Turin stepping per board revision and follow the vendor thermal manual for the exact heatsink, shroud and airflow direction.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 128 cores the memory per core is the tightest in the classic line, so fully populated high-capacity DIMMs matter more here than anywhere else in Turin. The board memory guide sets legal mixes for the 500 W envelope and 2DPC fallbacks.

PCIe 5.0 x128 lanes per socket with CXL 2.0 serve NVMe fleets, networking and accelerators across both CPUs. Dense hosts often attach the most NVMe per socket in the fleet, and lane planning should reserve paths for every drive. CXL expanders add a slower tier where datasets exceed DIMM capacity.

Cooling at 500 W needs vendor-qualified high-performance air for tall chassis or direct liquid cooling for dense racks. No tray cooler ships. Dual-socket 500 W pairs demand balanced airflow across both processors, so commissioning should validate clocks under the real guest mix.

Upgrade paths

Inside SP5 the 9755 is the top of the classic-core ladder: upgrades arrive from the 96-core AMD EPYC 9655 or 64-core AMD EPYC 9555 when guest density maxes out, keeping boards and memory with a BIOS check while power steps to 500 W. Cache doubles from 256 MB to 512 MB against the 64-core step.

The dense-core alternative is the Zen 5c line such as the AMD EPYC 9965 with 192 cores at lower clocks for thread-first hosting. Leaving SP5 entirely waits for later sockets with fresh memory qualification.