AMD EPYC 9555P socket: SP5

What the EPYC 9555P is

The EPYC 9555P is a 64-core, 128-thread server processor that AMD released on October 10, 2024 for single-socket Turin systems. Zen 5 cores run at 3.2 GHz base with boost to 4.4 GHz and all-core boost at 4.2 GHz. Shared L3 cache totals 256 MB across eight compute dies of about 70.6 sq mm each. Default TDP is 360 W configurable between 320 and 400 W.

The P suffix marks 1P platforms: the AMD EPYC 9555 matches it on cores, clocks, cache and power but scales to two sockets, while the 9555P is qualified for single-socket boards at lower platform cost. Buyers who never add a second socket avoid paying for dual-socket board complexity. The embedded twin AMD EPYC Embedded 9555P serves industrial carriers. Eight CCDs of 8 cores each keep the topology uniform for predictable guest placement.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. With 128 threads in one socket and no inter-socket hops, latency-sensitive guests run at their most predictable. Virtual desktop brokers often standardize on 1P 64-core hosts because the per-desktop cost stays flat as users grow.

Socket and motherboard compatibility

The 9555P fits the SP5 socket in FC-LGA6096 packaging on single-socket server boards with 360 W delivery. Only 1P board designs qualify, even though the socket matches dual-capable platforms built for higher envelopes. The board maker CPU support list confirms the SKU with its minimum BIOS.

Choosing P over non-P happens at purchase: 1P boards cost less with simpler NUMA layout, while 2P boards with the AMD EPYC 9555 keep expansion open. Memory bandwidth per core is identical at 12 channels either way. Licensing models that charge per socket favor the P line wherever a second socket adds no value. Colocation customers like 1P hosts because per-U billing stays predictable.

Genoa-era boards generally accept Turin after a firmware update with validated stepping support. Confirm stepping support per board revision rather than assuming the socket alone guarantees boot on every chassis. Mixed P and non-P fleets share firmware and management tooling for simpler daily administration.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB in one socket. Single-socket hosts concentrate guests behind one memory system, so fully populated channels matter for consistent performance. The board memory guide sets legal DIMM mixes for the 360 W envelope and warm data halls. Database consolidation on 1P hosts should size memory for the full dataset up front, since single-socket bandwidth has no second CPU to share the load.

PCIe 5.0 x128 lanes with CXL 2.0 serve NVMe, networking and accelerators from the single CPU without inter-socket links. Slot bifurcation follows the 1P board layout. Uniform latency across all devices is the architectural payoff of one socket. AI inference nodes often pair one GPU with direct-attached NVMe on 1P boards to keep the data path short and predictable.

Cooling at 360 W needs vendor-qualified air or liquid heatsinks for the chassis height and airflow pattern. No tray cooler ships. Single-socket 1U designs need airflow qualification at this power, so follow the vendor thermal manual for heatsink and shroud selection.

Upgrade paths

Inside single-socket SP5 the 9555P grows from smaller P SKUs when guest density rises, keeping board and memory with a BIOS check while power steps to 360 W. Larger 1P options such as the AMD EPYC 9655P add threads at 400 W for denser hosts. Operators should revalidate thermal margins after any step up in power class during maintenance windows.

Moving to dual-socket means new boards with the AMD EPYC 9555 instead for expansion headroom. Leaving SP5 entirely waits for later sockets with fresh memory qualification and new board designs.