AMD EPYC Embedded 9015 socket: SP5

What the AMD EPYC Embedded 9015 is

The AMD EPYC Embedded 9015 is the 8-core entry model of the EPYC Embedded 9005 Turin stack on Socket SP5. It runs 16 threads at 3.6 GHz base with boost to 4.1 GHz, backed by 64 MB of L3 cache and a 125 W default TDP. AMD announced the Embedded 9005 series on March 11, 2025 with production shipments expected in the second quarter of 2025, building the Zen 5 chiplets on a 4 nm process with a 6 nm I/O die.

Eight cores at high base clocks suit small gateways, timing servers, retail controllers and single-function appliances where license cost and power draw matter more than thread count. The 64 MB L3 pool keeps control plane and packet work near the cores without reaching out to DRAM on every lookup. At 125 W the part fits compact short-depth chassis and quieter airflow profiles.

Against the 16-core AMD EPYC Embedded 9135 above it, the 9015 halves the core count for sites that pay per core or per watt and run one steady workload. Against older 8-core Genoa parts, it adds higher boost behavior and Turin firmware with long-life support. The 7-year manufacturing window suits industrial qualification. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Socket and motherboard compatibility

The 9015 fits Socket SP5, a 6,096-contact land grid array that AMD built for EPYC 9004 Genoa and EPYC 9005 Turin processors. Boards support one or two sockets with this non-P part, though a single 9015 fills most target appliances and there is rarely a reason to pair two 8-core parts. SP5 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor.

Turin shares SP5 packaging with Genoa, so many Genoa boards take the 9015 after a BIOS update from the board maker at the same power class. A 9015 at 125 W sits at the low end of the SP5 power range, which keeps the swap simple where the vendor lists Turin support. Memory on an older board may stay at the Genoa qualified speed rather than reaching DDR5-6000, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP5 socket feeds 12 DDR5 channels with ECC RDIMM or 3DS RDIMM modules, and AMD rates Turin to 6000 MT/s with 6400 MT/s in target configs for up to 6 TB per socket. Small 9015 nodes often populate 4 or 8 channels to match the workload, which trims cost while keeping ECC protection. Population order varies by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 5 with x128 lanes per socket, plus x8 Gen 3 lanes for board devices and slower slots. Even an 8-core node can use the full lane budget for NVMe storage, networking and timing cards, since lanes come from the I/O die rather than the core count. CXL 2.0 memory expansion is part of the Turin platform where the board wires it, and bifurcation follows board firmware.

Cooling follows the board vendor list rather than a retail box. SP5 uses server retention with heatsinks validated per TDP class, and the 9015 at 125 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a fanless or outdoor cabinet demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9015 starts with the 16-core AMD EPYC Embedded 9135 and the 24-core AMD EPYC Embedded 9255, all staying on SP5 boards where power and cooling allow. The 32-core AMD EPYC Embedded 9355 follows for busier sites on the same board family. Each move keeps board and memory investments where the TDP class allows, plus a BIOS that already supports Turin.

There is no smaller Turin embedded part below the 9015, so a lower power target means a different platform such as AM5 entry servers or small BGA edge boards. That change replaces board, memory population and cooling design from scratch. The decision turns on whether the node needs SP5 lanes and channels or fits a compact low-power board.