AMD EPYC 9555 socket: SP5

What the EPYC 9555 is

The EPYC 9555 is a 64-core, 128-thread server processor that AMD released on October 10, 2024 with the 5th Gen EPYC 9005 series. It uses Zen 5 cores from the Turin family at 3.2 GHz base with boost to 4.4 GHz and all-core boost at 4.2 GHz. Shared L3 cache totals 256 MB across eight compute dies. Default TDP is 360 W configurable between 320 and 400 W.

Inside the Turin stack the 9555 is the balanced 64-core choice: fewer cores than the 96-core AMD EPYC 9655 with higher base clocks for mixed virtualization and database duty. Against the single-socket AMD EPYC 9555P the silicon matches while platform support differs, since the non-P SKU scales to two sockets. The embedded twin AMD EPYC Embedded 9555 carries the same core count to industrial boards. Configurable TDP lets operators trade sustained clocks for rack power limits without changing SKUs.

There is no integrated graphics and the multiplier is locked, which is standard for this class. ECC memory rides on DDR5 RDIMMs. Two threads per core give 128 threads per socket for the hypervisor to schedule. Eight CCDs of 8 cores each keep the topology uniform, which helps NUMA-aware guests place memory close to compute.

Socket and motherboard compatibility

The 9555 fits the SP5 socket, the 6,096-contact LGA platform for Genoa, Bergamo and Turin EPYC processors. The package is FC-LGA6096. Server boards qualified for the 360 W class accept it with a BIOS that lists Turin stepping and the required AGESA version. Boards built for Genoa generally carry over with a firmware update rather than new hardware purchases.

Scaling covers one or two sockets per system. Single-socket-only boards take the P-series SKUs such as the AMD EPYC 9555P instead, while the 9555 serves both single and dual layouts. Before ordering, confirm the exact SKU on the board maker CPU support list with the minimum BIOS revision.

Buyers comparing vendors weigh per-core speed against density: Turin P-cores here against dense-cloud alternatives on other sockets. Within SP5 the choice is clocks and cache per dollar, since the socket and memory generation stay constant.

Memory, PCIe and cooling

Memory support is DDR5 up to 6400 MT/s in 12 channels per socket with ECC RDIMMs, to 6 TB per socket. Twelve populated channels feed 64 cores with about 614 GB/s of theoretical bandwidth. The database rates standard operation at 6000 MT/s with 6400 reachable in single-DIMM-per-channel layouts, so populate evenly and read the board memory guide for the exact matrix. Database and virtualization hosts should favor capacity planning first, since 6 TB ceilings decide consolidation ratios before core counts do.

PCIe 5.0 lanes number 128 per socket with CXL 2.0 for memory expansion and accelerators. NVMe fleets, fast networking and GPU cards attach directly to CPU lanes, while board devices sit behind the platform hub. Lane splits per slot follow the board design and its BIOS options.

Cooling at 360 W uses vendor-qualified air and liquid server heatsinks matched to chassis height. No cooler ships with the tray processor. The board vendor thermal manual sets the approved list, including 1U, 2U and direct-liquid options for dense racks.

Upgrade paths

On the same socket the path up from the 9555 leads to the 96-core AMD EPYC 9655 for virtual machine density or to frequency-optimized F SKUs such as the AMD EPYC 9175F for licensed per-core speed. Boards, memory and PCIe cards carry over with a BIOS check, while power and cooling step to the higher envelope.

Lateral moves include the single-socket AMD EPYC 9555P for 1P-only boards at the same core count. Leaving SP5 entirely means new boards on a later socket with fresh memory qualification, so it normally waits for a refresh cycle.