AMD EPYC 9535 socket: SP5

What the EPYC 9535 is

The EPYC 9535 is a 64-core, 128-thread server processor that AMD released on October 10, 2024 with Turin. Zen 5 cores run at 2.4 GHz base with boost to 4.3 GHz and all-core boost at 3.5 GHz. Shared L3 cache totals 256 MB across eight compute dies. Default TDP is 300 W configurable between 240 and 300 W.

Low base clocks with a full 64 cores define the efficiency play: the same thread count as the AMD EPYC 9555 at lower sustained power for hosts that idle generously between bursts. Against the 48-core AMD EPYC 9455 nearby it adds 16 cores for denser guests at matching power. The 2.4 GHz base sips power while 4.3 GHz boost answers interactive logins without delay for users and automation alike across every shift.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction. Two threads per core give 128 threads per socket for guest placement and burst handling across all tenants. Operators with variable loads favor this SKU because idle efficiency matters more than peak clocks there.

Workload fit is efficient density: private clouds with bursty tenants, development clusters that sleep at night, and branch hosts that must cover peaks without paying for sustained speed. Operators pick the 9535 over the 9555 where average draw sits far below TDP, since the lower base clock converts directly into cooler racks and quieter fans.

Socket and motherboard compatibility

The 9535 fits the SP5 socket in FC-LGA6096 packaging on 300 W-class server boards. Genoa boards accept Turin after a firmware update with the new stepping. The board maker CPU support list confirms the SKU with its minimum BIOS, and power stages assume the upper configurable bound with margin for transients.

One or two sockets are supported. Efficient 64-core hosts suit buyers who want thread count without the power bill of faster SKUs: two sockets give 128 cores with 24 memory channels for bursty clouds. Socket-count licensing treats both sockets like any other Turin pair for predictable budgeting.

Genoa-era boards generally accept Turin after a firmware update with validated stepping support for production fleets. Mixed fleets of efficient and dense SKUs share firmware trains and spares across both for simpler operations and on-call rotations.

Memory, PCIe and cooling

DDR5 up to 6400 MT/s in 12 channels with ECC RDIMMs reaches 6 TB per socket. At 64 efficient cores the memory per core supports memory-sized guests beside bursty tenants. Fully populated channels with matched DIMMs keep bandwidth uniform. The board memory guide sets legal mixes for the 300 W envelope and warm data halls.

PCIe 5.0 x128 lanes per socket with CXL 2.0 attach NVMe fleets, networking and accelerators. Slot widths follow the board design with exact splits in the manual for each chassis variant. CXL expanders add capacity tiers for hosts whose datasets exceed DIMM limits during peak quarters.

Cooling at 300 W uses vendor-qualified air or liquid heatsinks per chassis with validated airflow paths. No tray cooler ships. Average draw well below TDP keeps real-world thermals gentle, though qualification should still cover sustained all-core peaks before production sign-off and tenant onboarding..

Upgrade paths

Within SP5 the 9535 grows from the 48-core AMD EPYC 9455 for threads at matching power or trims from the 64-core AMD EPYC 9555 for efficiency, reusing boards and memory. Each move needs only a BIOS check with matching cooling. Power capping policies deserve a recheck after any swap between power classes.

Frequency-optimized F SKUs serve per-core speed on the same boards at higher power for licensed database tiers. A full platform exit waits for post-SP5 sockets with fresh memory qualification for future clusters.