AMD EPYC Embedded 9255 socket: SP5

What the AMD EPYC Embedded 9255 is

The AMD EPYC Embedded 9255 is the 24-core member of the EPYC Embedded 9005 Turin stack on Socket SP5. It runs 48 threads at 3.2 GHz base with boost to 4.3 GHz, backed by 128 MB of L3 cache and a 200 W default TDP. AMD announced the Embedded 9005 series on March 11, 2025 with production shipments expected in the second quarter of 2025, building the Zen 5 chiplets on a 4 nm process with a 6 nm I/O die.

Twenty-four cores at a 200 W envelope suit remote gateways, entry storage nodes, test beds and industrial controllers where power and cooling budgets stay modest. Base clocks above 3 GHz keep control plane and firewall threads responsive, while 48 threads cover bursts without reaching for a larger socket. The 128 MB L3 pool keeps packet and metadata work near the cores.

Against the 16-core AMD EPYC Embedded 9135 below it, the 9255 adds 8 cores and doubles the L3 for busier edge sites. Against the 32-core AMD EPYC Embedded 9355 above it, the 9255 keeps a lower 200 W class for compact chassis. Long-life firmware and 7-year manufacturing support suit qualified appliances. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Socket and motherboard compatibility

The 9255 fits Socket SP5, a 6,096-contact land grid array that AMD built for EPYC 9004 Genoa and EPYC 9005 Turin processors. Boards support one or two sockets with this non-P part, so one 9255 fills a compact appliance or pairs with an identical 9255 in a dual-socket node. SP5 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor.

Turin shares SP5 packaging with Genoa, so many Genoa boards take the 9255 after a BIOS update from the board maker at the same power class. A 9255 at 200 W fits boards already rated for 200 W Genoa parts, which keeps thermals and power delivery inside known limits. Memory on an older board may stay at the Genoa qualified speed rather than reaching DDR5-6000, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP5 socket feeds 12 DDR5 channels with ECC RDIMM or 3DS RDIMM modules, and AMD rates Turin to 6000 MT/s with 6400 MT/s in target configs for up to 6 TB per socket. Even a 24-core part benefits from 12 channels when packet buffers and storage caches grow. Population order and maximum capacity vary by board, so the vendor memory list governs every build, and dual-socket builds use matched DIMM populations.

PCI Express connectivity is Gen 5 with x128 lanes per socket, plus x8 Gen 3 lanes for board devices and slower slots. That lane budget feeds NVMe pools, 25 and 100-gigabit networking and accelerator cards on an edge node without lane sharing pressure. CXL 2.0 memory expansion is part of the Turin platform where the board wires it, and bifurcation follows board firmware, so architects confirm slot maps before committing to a network-heavy layout.

Cooling follows the board vendor list rather than a retail box. SP5 uses server retention with heatsinks validated per TDP class, and the 9255 at 200 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a fanless or outdoor cabinet demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9255 starts with the 32-core AMD EPYC Embedded 9355 and the 48-core AMD EPYC Embedded 9455P, all staying on SP5 boards where power and cooling allow. The 64-core AMD EPYC Embedded 9535 follows for denser consolidation on the same board family. Each move keeps board and memory investments where the TDP class allows, plus a BIOS that already supports Turin.

The path down to the 16-core AMD EPYC Embedded 9135 and the 8-core AMD EPYC Embedded 9015 trims power to 200 W and below for small outdoor or retail nodes. A move to AM5 entry servers is a different platform with 2 memory channels and lower power classes. That change replaces board, memory population and cooling design from scratch. The choice turns on per-site power against thread count.