AMD EPYC Embedded 9755 socket: SP5

What the AMD EPYC Embedded 9755 is

The AMD EPYC Embedded 9755 is the 128-core Zen 5 flagship of the classic-core Embedded 9005 Turin stack on Socket SP5. It runs 256 threads at 2.7 GHz base with boost to 4.1 GHz, backed by 512 MB of L3 cache and a 500 W default TDP. AMD announced the Embedded 9005 series on March 11, 2025 with production shipments expected in the second quarter of 2025, building the Zen 5 chiplets on a 4 nm process with a 6 nm I/O die.

One hundred twenty-eight full-size cores suit dense virtualization hosts, software-defined storage clusters, data firewalls and industrial private clouds that consolidate many services per socket. The 512 MB L3 pool is the largest in the classic-core embedded range, which helps large working sets stay near the cores. Twelve DDR5 channels feed the thread count, and 7-year manufacturing support suits long telecom qualification cycles.

Against the 96-core AMD EPYC Embedded 9655 below it, the 9755 adds 32 cores and 128 MB of L3 for sites that pay per rack unit. Against the dense-core AMD EPYC Embedded 9745 beside it, the 9755 keeps full-size Zen 5 cores with higher per-core clocks rather than maximizing thread count. Power and cooling decide between them more than socket fit. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Socket and motherboard compatibility

The 9755 fits Socket SP5, a 6,096-contact land grid array that AMD built for EPYC 9004 Genoa and EPYC 9005 Turin processors. Boards support one or two sockets with this non-P part, so one 9755 fills a dense appliance or pairs with an identical 9755 in a dual-socket rack node. SP5 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor.

Turin shares SP5 packaging with Genoa, but a 500 W part narrows the list of ready boards. Only chassis and power delivery rated for the 500 W class can take the 9755, and the BIOS must list Turin explicitly. Memory may stay at the older qualified speed on a carryover board rather than reaching DDR5-6000, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP5 socket feeds 12 DDR5 channels with ECC RDIMM or 3DS RDIMM modules, and AMD rates Turin to 6000 MT/s with 6400 MT/s in target configs for up to 6 TB per socket. Twelve channels at these rates keep 256 threads supplied in virtualization, database and storage mixes. Population order and maximum capacity vary by board, so the vendor memory list governs every build, and dual-socket builds use matched DIMM populations.

PCI Express connectivity is Gen 5 with x128 lanes per socket, plus x8 Gen 3 lanes for board devices and slower slots. That lane budget feeds all-flash arrays, 100-gigabit and faster networking and accelerators on a dense node without lane sharing pressure. CXL 2.0 memory expansion is part of the Turin platform where the board wires it, and bifurcation follows board firmware, so architects confirm slot maps before committing to a consolidation layout.

Cooling follows the board vendor list rather than a retail box. SP5 uses server retention with heatsinks validated per TDP class, and the 9755 at 500 W needs liquid or high-airflow kits rated for that class in the intended chassis. No cooler ships with the processor. Firmware power limits can cap draw below the default where a site demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the dense-core AMD EPYC Embedded 9745, AMD EPYC Embedded 9845 and AMD EPYC Embedded 9965 raise thread count further on SP5 boards where throughput matters more than per-core clocks. Each keeps the same 12-channel memory and PCIe layout, plus a BIOS that already supports Turin. The move suits racks that bill by cores per unit rather than by frequency.

The step down to the 96-core AMD EPYC Embedded 9655 trims power to 400 W while keeping full-size Zen 5 cores. A move to AM5 entry servers is a different platform with 2 memory channels and far lower power classes. That change replaces board, memory population and cooling design from scratch. The decision turns on density against power budget per rack.