AMD Ryzen AI Embedded P132 socket: FP8

What the Ryzen AI Embedded P132 is

The Ryzen AI Embedded P132 is the 6-core member of the P100 series, launched with the 4-to-6-core range in January 2026 for automotive cockpits and industrial HMIs. Two Zen 5 cores plus four Zen 5c cores give 12 threads with boost to 4.5 GHz, cache is 6 MB of L2 with 8 MB of L3, and graphics are 4 RDNA 3.5 compute units at up to 2800 MHz. The XDNA 2 NPU offers up to 50 TOPS. Default TDP is 28 W inside the 15 to 54 W configurable range on TSMC 4 nm.

The 6-core point serves designs where determinism and graphics matter more than thread count: digital cockpits driving up to four 4K displays, machine HMIs with local inference, and gateways with 10-gigabit time sensitive networking, which this SKU carries on die. The smaller GPU and narrower PCIe allocation fit the lighter CPU, and the whole chip stays in the same 28 W default as its bigger siblings.

Embedded terms match the series: continuous operation rating, 10-year supply with last time buy in 2036, and production shipments in the second quarter of 2026 after sampling with early customers. Standard grade spans 0 to 105 degrees junction, and the AMD Ryzen AI Embedded P132i extends the low end to minus 40.

Socket and board compatibility

The P132 solders into FP8, the 25 × 40 mm BGA shared from Phoenix through Gorgon Point. The joint is permanent, so SKU, memory size and thermals are fixed per build. Production modules come from Advantech, congatec, Kontron and others, with chip-down layouts for volume.

Package sharing helps board reuse, but firmware must name the APU, so carriers need updates listing the P132. Documentation and tools were available from the January launch.

Within the series the 8-core models add CPU and graphics above on the same package, while 4-core parts cut further for the smallest budgets. The Halo class FP11 X100 series stands beyond FP8 for heavy designs.

Memory, PCIe and cooling

Boards use DDR5-5600 modules or soldered LPDDR5X up to 8000 MT/s, dual channel with ECC and Link-ECC options. The ceiling sits below the 8533 of the bigger Gorgon SKUs, which matches the lighter memory demands of six cores and four graphics units. Soldered capacity cannot grow later.

I/O is generous for the class: 14 PCIe Gen4 lanes, two USB4 ports, USB 3.2 and 2.0, four display outputs to 7680x4320, and 10-gigabit Ethernet with time sensitive networking for deterministic industrial links. Lanes feed NVMe, networking and sensors per board manual. The 4 compute unit graphics engine covers cockpit and HMI display without a discrete card.

Cooling is a system design for the configured TDP between 15 and 54 W on the lidless package. The 28 W default suits fanless enclosures, and sustained operation should be validated at continuous power. No boxed cooler exists.

Platform, software and lifecycle

AMD launched the 4-to-6-core P100 parts first, in January 2026, for in-vehicle experiences and industrial automation that need real-time graphics with AI beside them. The stack supports Linux, Xen, Android Automotive on these smaller SKUs, FreeRTOS and ROCm, with partitioning for mixed criticality designs. Compared with the previous Embedded 8000 series, AMD positions the range at large multithreaded and system TOPS gains.

The 10-year lifecycle to 2036 protects automotive and industrial programs from requalification, and AEC-Q100 qualification covers the automotive grades in this class.

Upgrade paths

Soldered packages cannot be upgraded. A new build around a larger or smaller P100 SKU is the only move inside FP8, and Halo X100 parts need FP11 boards. Desktop Gorgon class silicon uses AM5.

Choose SKU and memory for the lifetime workload at the start, since neither changes in the field.