AMD EPYC 7352 socket: SP3
The AMD EPYC 7352 uses SP3, the LGA socket for EPYC server processors. The 24-core chip at 155 W targets dense efficient clusters.
AMD EPYC 7352 specifications
| Cores | 24 |
|---|---|
| Threads | 48 |
| Core architecture | Zen 2 (Rome) |
| Clocks | 2.3 GHz base, up to 3.2 GHz boost |
| Cache | 12 MB L2 plus 128 MB L3 |
| Default TDP | 155 W |
| Manufacturing process | TSMC 7 nm FinFET |
| Memory support | DDR4-3200 ECC, 8 channels |
| PCI Express | 128 PCIe Gen4 lanes per socket, up to 160 in 2P |
| Integrated graphics | None (BMC graphics on board) |
| Multiplier | Locked |
| ECC memory | Supported, DDR4 ECC RDIMM |
| Package | SP3 LGA4094 |
| Cooler in the box | None, server heatsink required |
Motherboard compatibility
AMD EPYC 7352 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7352 is
The EPYC 7352 is a 24-core, 48-thread server processor from Rome. It launched in August 2019 for dense efficient clouds with a 2.3 GHz base and up to 3.2 GHz boost at 155 W. Four chiplets share 128 MB of L3 across 24 cores.
The modest base clock stretches 24 cores inside a 155 W envelope for throughput per watt. Twelve megabytes of L2 back batch threads. Burst to 3.2 GHz keeps interactive tasks responsive.
Dual socket scaling reaches 48 cores per box for dense tenants. The 7352 undercuts the faster 7402 on price and power for throughput billing. Throughput clouds that charge per thread fit here.
Socket and motherboard compatibility
The EPYC 7352 fits SP3 on single and dual socket boards. Standard 155 W delivery covers it on most server boards. Vendor lists confirm firmware.
Dense dual socket pairs total 48 threads per node for hyperconverged blocks. Power capping can pin nodes lower where facilities demand. The How to find your CPU socket type guide maps server sockets.
Milan dense SKUs later continued the role on these boards with updates.
Memory, PCIe and cooling
Eight DDR4-3200 ECC channels feed 48 threads at full bandwidth. Dense nodes pair 512 GB with 24 cores. All channels filled avoids bandwidth starvation.
PCIe Gen4 lanes total 128 per socket for flash and networking. Dense tenants share lanes through switches where needed. Dual socket builds reach 160 lanes.
The 155 W class cools with standard dense heatsinks. No boxed cooler exists. Per core heat stays low across four chiplets.
Where this Rome part fits
Twenty four efficient cores fit web tiers, CI fleets and storage controllers billed by throughput. Low base clocks matter little for parallel batches. The 128 MB L3 smooths shared caches.
Colocation providers standardize on dual socket 7352 pairs for 48 cool cores. Pair with moderate RAM and 25 Gb networking. The AMD EPYC 7402 trades watts for base clocks nearby.
Confirm board power and thermals before filling racks with dense nodes.
Upgrade paths
On SP3 clocks grow to the 180 W 7402 on the same boards, or density grows to 32-core 7452. Milan dense parts follow with firmware.
SP5 platforms bring DDR5 density later. The CPU cooler compatibility by socket guide covers cooling classes.
Frequently asked questions
What socket does the AMD EPYC 7352 use?
It uses SP3 on single and dual socket server boards.
How many cores does the EPYC 7352 have?
24 cores with 48 threads at 2.3 GHz base and up to 3.2 GHz boost.
How much cache does the 7352 have?
12 MB of L2 plus 128 MB of L3.
What is the TDP of the EPYC 7352?
155 W with server cooling required.
When did the EPYC 7352 launch?
August 2019 with the Rome family.
Sources and verification
Facts last checked against these sources on . Page last edited on .