AMD EPYC 7552 socket: SP3
The AMD EPYC 7552 uses SP3, the LGA socket for EPYC server processors. The 48-core chip at 200 W serves dense throughput clusters.
AMD EPYC 7552 specifications
| Cores | 48 |
|---|---|
| Threads | 96 |
| Core architecture | Zen 2 (Rome) |
| Clocks | 2.2 GHz base, up to 3.3 GHz boost |
| Cache | 24 MB L2 plus 192 MB L3 |
| Default TDP | 200 W |
| Manufacturing process | TSMC 7 nm FinFET |
| Memory support | DDR4-3200 ECC, 8 channels |
| PCI Express | 128 PCIe Gen4 lanes per socket, up to 160 in 2P |
| Integrated graphics | None (BMC graphics on board) |
| Multiplier | Locked |
| ECC memory | Supported, DDR4 ECC RDIMM |
| Package | SP3 LGA4094 |
| Cooler in the box | None, server heatsink required |
Motherboard compatibility
AMD EPYC 7552 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7552 is
The EPYC 7552 is a 48-core, 96-thread server processor from Rome. It launched in August 2019 for dense throughput with a 2.2 GHz base and up to 3.3 GHz boost at 200 W. Six chiplets share 192 MB of L3.
Forty eight cores per socket consolidate virtualization farms onto fewer nodes. Twenty four megabytes of L2 back batch threads. The modest base clock reflects power sharing, while burst still lifts interactive tasks.
Dual socket scaling reaches 96 cores per box for dense private clouds. The 7552 undercuts the 7642 on price and cache for throughput billing. Throughput clouds that count threads fit here.
Socket and motherboard compatibility
The EPYC 7552 fits SP3 on single and dual socket boards with 200 W delivery. Dense boards need strong power stages for 48 cores. Vendor lists confirm firmware.
Hyperconverged blocks standardize on dual socket 7552 pairs for 96 threads per node. Redundant cooling zones matter at this density. The How to find your CPU socket type guide maps server sockets.
Milan 48-core parts later continued dense roles on these boards with updates.
Memory, PCIe and cooling
Eight DDR4-3200 ECC channels feed 96 threads at full bandwidth. Dense nodes pair 1 TB with 48 cores for VM farms. All channels filled avoids bandwidth collapse.
PCIe Gen4 lanes total 128 per socket for flash and networking. Dense tenants share lanes through switches. Dual socket builds reach 160 lanes.
The 200 W class needs premium air or liquid cooling. No boxed cooler exists. Per core heat stays modest across six chiplets.
Where this Rome part fits
Forty eight cores fit virtual desktop farms, web tiers and storage controllers billed by density. Thread count beats clocks for parallel batches. The 192 MB L3 smooths shared working sets.
Providers standardize on dual socket 7552 pairs with 25 Gb networking. Pair with high capacity NVMe for dense tenants. The AMD EPYC 7642 adds cache and clocks nearby for mixed loads.
Confirm board thermals before filling racks with 200 W nodes.
Upgrade paths
On SP3 density grows to 64-core 7702 parts on the same boards, or Milan 48-core SKUs for IPC. Memory and flash carry over.
SP5 platforms bring DDR5 density later. The CPU cooler compatibility by socket guide covers 200 W cooling.
Frequently asked questions
What socket does the AMD EPYC 7552 use?
It uses SP3 on single and dual socket server boards.
How many cores does the EPYC 7552 have?
48 cores with 96 threads at 2.2 GHz base and up to 3.3 GHz boost.
How much cache does the 7552 have?
24 MB of L2 plus 192 MB of L3.
What is the TDP of the EPYC 7552?
200 W with server cooling required.
When did the EPYC 7552 launch?
August 2019 with the Rome family.
Sources and verification
Facts last checked against these sources on . Page last edited on .