AMD EPYC 7302 socket: SP3
The AMD EPYC 7302 uses SP3, the LGA socket for EPYC server processors. The 16-core chip at 155 W balances clocks and density.
AMD EPYC 7302 specifications
| Cores | 16 |
|---|---|
| Threads | 32 |
| Core architecture | Zen 2 (Rome) |
| Clocks | 3.0 GHz base, up to 3.3 GHz boost |
| Cache | 8 MB L2 plus 128 MB L3 |
| Default TDP | 155 W |
| Manufacturing process | TSMC 7 nm FinFET |
| Memory support | DDR4-3200 ECC, 8 channels |
| PCI Express | 128 PCIe Gen4 lanes per socket, up to 160 in 2P |
| Integrated graphics | None (BMC graphics on board) |
| Multiplier | Locked |
| ECC memory | Supported, DDR4 ECC RDIMM |
| Package | SP3 LGA4094 |
| Cooler in the box | None, server heatsink required |
Motherboard compatibility
AMD EPYC 7302 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7302 is
The EPYC 7302 is a 16-core, 32-thread server processor from Rome. It launched in August 2019 as the high clock 16-core option with a 3.0 GHz base and up to 3.3 GHz boost at 155 W. Four chiplets feed 128 MB of L3, double the cache of the efficient 7282.
The 3.0 GHz base leads general virtualization hosts for latency sensitive tenants. Eight megabytes of L2 back mixed threads. The extra 35 W over the 7282 buys sustained clocks under load.
Dual socket scaling reaches 32 fast cores per box for mainstream clouds. The 7302 sits at the center of the Rome stack for buyers who want no compromises at 16 cores. Its single socket twin 7302P serves the same clocks in 1P boards.
Socket and motherboard compatibility
The EPYC 7302 fits SP3 on single and dual socket boards with 155 W delivery. Vendor qualification covers thermals at this band. Rome firmware posts it natively.
Mainstream dual socket pairs total 32 cores for cloud regions. Heatsinked power stages hold boost through long jobs. The How to find your CPU socket type guide explains server sockets.
Milan 16-core parts later dropped into these boards with BIOS updates for IPC gains.
Memory, PCIe and cooling
Eight channels of DDR4-3200 ECC move data at up to 204.8 GB per sec. Full populations suit memory hungry VMs. ECC corrects errors during long uptimes.
PCIe Gen4 lanes total 128 per socket for NVMe and 100 Gb networking. Mainstream clouds attach flash pools without switches. Dual socket builds reach 160 lanes.
The 155 W heatsink class needs front to back airflow in 1U. No boxed cooler exists. Cool inlets preserve boost best.
Where this Rome part fits
Sixteen fast cores with huge cache fit virtualization, databases and build fleets that need both latency and density. The 3.0 GHz base avoids the tail latency of slower dense parts. One hundred twenty eight megabytes of L3 absorb shared working sets.
Cloud regions standardize on dual socket 7302 pairs with a terabyte of RAM. All eight channels filled matters for analytics. The AMD EPYC 7282 trims watts nearby for power capped rows.
Buyers confirm power delivery and firmware with the vendor before dense rollouts.
Upgrade paths
On SP3 density grows to 24-core 7402 parts on the same boards, or Milan 16-core SKUs for IPC. Memory and NVMe carry over.
SP5 Genoa servers bring DDR5 for next generation density. The CPU cooler compatibility by socket guide details cooling bands.
Frequently asked questions
What socket does the AMD EPYC 7302 use?
It uses SP3 on single and dual socket server boards.
How much cache does the 7302 have?
8 MB of L2 plus 128 MB of L3.
How is the 7302 different from the 7282?
Higher 3.0 GHz base clocks with double the L3 at 155 W against 120 W.
Does the 7302 scale dual socket?
Yes. It runs one or two sockets.
What is the TDP of the EPYC 7302?
155 W with server cooling required.
When did the EPYC 7302 launch?
August 2019 with the Rome stack.
Sources and verification
Facts last checked against these sources on . Page last edited on .