VIA C7 1.5 socket: VIA NanoBGA2

What the C7 1.5 is

The VIA C7 1.5 is a 1500 MHz single-core soldered embedded processor from May 2005. It runs one Centaur Esther core at 1500 MHz with no turbo, so 1 core gives 1 thread. Cache is 128 KB of L2 with 128 KB of L1 on a 90 nm SOI process at IBM. Power is rated at 12 W in a NanoBGA2 soldered package on a 400 MT/s bus with a 15x multiplier.

Doubled L2 over C3 Nehemiah parts with SSE2, SSE3 and NX bit support gives the C7 1.5 modern instruction paths that C3 boards lack, which is why the 1.5 suits thin clients with current software. VIA launched Esther on May 27, 2005. The chip supports MMX, SSE through SSE3, NX bit and PadLock security with PowerSaver states.

A 1.5 GHz clock with a 12 W envelope suits fanless thin clients with DDR2 memory. The 30 square mm die sips power at idle down to 0.1 W. That is why the C7 1.5 shipped in green mini PCs.

Socket and motherboard compatibility

The C7 1.5 is soldered to NanoBGA2 boards and cannot be replaced. It fits embedded boards with NanoBGA2 solder lands and firmware that lists VIA C7 parts. The Socket vs chipset: what decides whether a CPU works guide covers pairing rules.

Fanless thin client boards are the natural match. Boards built for the C7 1.5 carry the soldered chip with a board spreader for the 12 W class.

Memory, PCIe and cooling

Memory is DDR2 through the board chipset, matched to the embedded board. The soldered CPU has no memory controller of its own beyond the VIA V4 bus to the chipset. Thin boards commonly pair DDR2-400 pairs.

A 400 MT/s VIA V4 bus ties the soldered chip to the chipset, while expansion hangs off the chipset. No PCIe lanes originate on the die in most layouts. Thermal design is board-level with a spreader.

Upgrade paths

There is no CPU upgrade path from a soldered C7 1.5. The chip cannot move to a faster part. A board replacement is the only move.

For planning, a C7 2.0 on the same NanoBGA2 lands adds 500 MHz at 20 W when the board lists it. The VIA NanoBGA2 page lists the Esther range.