AMD EPYC Embedded 9354 socket: SP5

What the EPYC Embedded 9354 is

The EPYC Embedded 9354 is the 32-core workhorse of Genoa embedded for SP5 in March 2023. Thirty-two Zen 4 cores with multithreading run at 3.25 GHz base and up to 3.8 GHz boost with 3.75 GHz all-core boost, backed by 32 MB of L2 and 256 MB of L3. Four CCDs plus the IOD form the package on TSMC 5 nm with a 280 W default inside a 240 to 300 W window. It suits edge servers that need balanced threads and clocks with long supply.

Midrange density with high clocks suits virtualised edge clouds and network functions that mix control and data planes. Thirty-two cores share 256 MB of L3 for VM locality, while 12 DDR5-4800 ECC channels feed 6 TB per socket. One hundred twenty-eight Gen5 lanes per socket keep NICs and NVMe fed for single and dual socket nodes.

Buyers step to the 9354 from 24-core parts for higher VM counts without jumping to 64-core power. It matches the server 9354 in silicon but adds embedded qualification for multi-year edge fleets. Smaller nodes stay with fewer cores on the same SP5 base. The Socket vs chipset: what decides whether a CPU works guide is secondary to board firmware lists for embedded fit.

Socket and motherboard compatibility

The Embedded 9354 fits SP5 on single or dual socket embedded boards with LGA 6096 frames. Board lists must name Genoa Embedded 9004 for boot support. Power delivery for 280 W continuous with lower cTDP options suits edge chassis that cannot cool 360 W flagships.

SP5 boards wire 12 DDR5 channels per socket with flexible populations for cost control. BMC firmware covers remote management for far-flung nodes. Confirm heatsink and PSU sizing for sustained all-core loads before consolidating workloads.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels to 6 TB per socket feeds 32 cores for edge consolidation. Two to twelve channel options tune small and large configs. ECC stays enabled for edge uptime. Validated kits at rated speed are required for 12-channel stability.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket plus CXL for accelerators. A 32-core node typically wires several NICs and NVMe arrays. Cooling needs an SP5 server sink for 280 W with front-to-back flow. Lower cTDP settings help hot sites at the cost of clocks.

Upgrade paths

On SP5 the upward moves are 48-core and 64-core Genoa embedded parts where VM density grows, without changing boards where power allows. Memory expansion to more channels and NIC additions often help more than cores for port growth. The 32-core point balances clocks and threads, so scaling tests should guide steps.

Outside SP5, Siena on SP6 lowers power for telco edge, while higher Genoa counts add density on SP5. Most Embedded 9354 owners add IO first, since 32 fast cores already cover midrange edge clouds.