AMD EPYC 9754S socket: SP5

What the EPYC 9754S is

The EPYC 9754S is the 128-core Bergamo variant that AMD lists with 128 threads for SP5 servers in June 2023. One hundred twenty-eight Zen 4c small cores run at 2.25 GHz base and up to 3.1 GHz boost without multithreading per the AMD product page, backed by 128 MB of L2 and 256 MB of L3. Eight 16-core CCDs plus the IOD form the package on TSMC 5 nm with a 360 W default. It shares Bergamo silicon with the 256-thread 9754 but targets workloads that prefer one thread per core.

Dense small cores with modest cache suit cloud-native scale-out where many single-thread workers run side by side. One thread per core trims contention for latency-sensitive front ends, data analytics and high-density VMs with small vCPUs. Twelve DDR5-4800 ECC channels feed 6 TB per socket, while 128 Gen5 lanes per socket feed fabric and NVMe. Power matches the threaded twin because core count dominates thermals.

Buyers compare the 9754S against the 9754 with 256 threads where SMT helps throughput. Single-thread-per-core operation can lift per-request consistency at the cost of peak throughput. Boards that run Genoa accept Bergamo with a BIOS update on the same SP5 socket. The Socket vs chipset: what decides whether a CPU works guide is secondary to board firmware lists.

Socket and motherboard compatibility

The 9754S fits SP5 on single or dual socket server boards with LGA 6096 frames. Board lists must name Bergamo 97x4 for Zen 4c support. Power delivery for 360 W continuous suits dense racks with strong airflow.

SP5 boards wire 12 DDR5 channels per socket with two DIMMs per channel for full capacity. BMC firmware covers fleet updates. Confirm heatsink class for 360 W with eight CCDs before consolidating scale-out workers.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 12 channels per socket to 6 TB feeds 128 small cores for dense VMs. Interleaving across channels tunes throughput. ECC stays enabled for fleet uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 128 lanes per socket and up to 160 in dual socket for fabric and NVMe. Scale-out nodes often wire high-radix networking with fast scratch. Cooling needs SP5 server sinks for 360 W with front-to-back data-centre flow.

Upgrade paths

On SP5 the sibling move is the 256-thread 9754 where SMT helps throughput without changing boards. Memory growth to 12 channels and fabric upgrades often help more than core changes for scale-out. The 128-core point already tops Bergamo density, so tuning thread policy beats chip swaps.

Outside Bergamo, Genoa adds cache per core and higher clocks on SP5, while Genoa-X adds stacked cache for HPC. Most 9754S owners tune SMT policy and memory first.