AMD EPYC Embedded 8534P socket: SP6

What the EPYC Embedded 8534P is

The EPYC Embedded 8534P is a 64-core, 128-thread embedded processor that AMD released on September 18, 2023 with the EPYC 8004 Siena family. Zen 4c dense cores run at 2.3 GHz base with boost to 3.1 GHz. Shared L3 cache totals 128 MB. Default TDP is 200 W configurable between 155 and 225 W.

A note on dates: the CPU list gives October 2024 for this SKU, but AMD launched the Siena family in September 2023, which this page follows as the authoritative date. Siena reuses the Bergamo 16-core Zen 4c chiplets with the same I/O die, so four chiplets cover the 64 cores with proven silicon qualified for long service. Against the 48-core AMD EPYC Embedded 8434P it adds 16 cores for denser edge tenants at matching power.

There is no integrated graphics and the multiplier is locked. ECC DDR5 RDIMMs carry correction across 6 channels. The P suffix marks single-socket platforms, and Siena serves single-socket designs only. A note on process: AMD charts do not print nanometers per SKU, so this page follows the shared Genoa and Bergamo die heritage at 5 nm compute with a 6 nm I/O die.

Workload fit is efficient edge density: telco data planes, retail and banking branch hosts, plus industrial gateways that need dozens of cores inside 200 W. Operators pick Siena where Turin SP5 exceeds power and board budgets but Bergamo-scale density still matters for edge tenants.

Socket and motherboard compatibility

The 8534P fits the SP6 socket in LGA-4844 packaging on single-socket edge boards. SP6 is Siena-only with 6 memory channels and 96 PCIe lanes, a smaller footprint than SP5 for cost-sensitive edge designs. The board vendor qualification list confirms the SKU with its minimum firmware for the 200 W envelope.

Single-socket only is the whole Siena story: no dual-socket boards exist for SP6, which simplifies NUMA layout to one node per system for predictable edge performance. Carriers and telco boards wire fast networking directly to CPU lanes, while industrial boards favor extended temperature validation and locking connectors.

Buyers choosing between Siena SKUs compare core count against per-core speed at fixed 200 W: the 8534P for density, the AMD EPYC Embedded 8434P for higher base clocks in clock-sensitive roles. Sockets, memory generation and PCIe generation match across both for common spares and shared qualification testing.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMMs in 6 channels reach 1.152 TB per socket. Six channels behind 64 cores is leaner than Turin ratios, so fully populated DIMMs matter for bandwidth-hungry packet work. The AMD SKU chart confirms the 4800 speed with 1DPC layouts for validated edge configurations. ECC suits unattended edge sites that reboot rarely and run far from technical staff.

PCIe 5.0 lanes number 96 per socket with a CXL subset for memory expansion on some designs. Telco carriers wire high-speed NICs directly to CPU lanes, while storage carriers split lanes across NVMe bays. Carrier manuals define the exact topology per vertical market.

Cooling at 200 W uses vendor-qualified air heatsinks for edge chassis classes. No tray cooler ships. The 155 to 225 W configurable band lets operators fit existing thermal designs without changing SKUs, which matters for refreshes inside deployed cabinets and street enclosures.

Upgrade paths

Inside SP6 the 8534P is the density top for its power: the 48-core AMD EPYC Embedded 8434P below trades cores for base clocks on the same carriers. Carrier firmware updates carry new SKUs where vendors validate them, which keeps chassis in service for years without recertification or hardware swaps.

A platform move beyond Siena means requalifying on newer embedded silicon with fresh longevity terms. Datacenter Turin parts share the Zen heritage but target different sockets and power classes, so cross-shopping them misses the edge-optimized purpose of this line.