AMD EPYC 8024P socket: SP6

What the EPYC 8024P is

The EPYC 8024P is the 8-core entry of Siena for single socket SP6 servers in September 2023. Eight Zen 4c small cores with multithreading run at 2.4 GHz base and up to 3.0 GHz boost with 2.95 GHz all-core boost, backed by 8 MB of L2 and 32 MB of L3. The TSMC 5 nm package targets 90 W inside a 70 to 100 W window for the lowest power Siena nodes. It suits retail, storage and gateway boxes that need server IO without many cores.

Few cores with full platform IO suit entry storage and IoT gateways that prize lanes and memory over threads. Eight cores share 32 MB of L3 for locality, while 6 DDR5-4800 ECC channels keep board cost down. Ninety-six Gen5 lanes serve networking and NVMe for single-socket designs. Low power allows compact chassis with modest cooling.

Buyers compare the 8024P against Xeon Bronze density parts where rack throughput per watt decides. Siena wins single-socket efficiency with 6 channels, while larger Siena parts add threads on the same SP6 base. Boards built for SP6 accept the full Siena stack with a BIOS update. The Socket vs chipset: what decides whether a CPU works guide is secondary to SP6 board lists.

Socket and motherboard compatibility

The 8024P fits SP6 on single socket server boards with LGA 4844 frames. Siena is 1P-only, so dual socket pairing is not supported. Board lists must name Siena 8004 for Zen 4c support. Power delivery for 90 W continuous with lower cTDP suits compact edge chassis.

SP6 boards wire 6 DDR5 channels with one DIMM per channel for best speed in many layouts. BMC firmware covers fleet management. Confirm heatsink height for short-depth nodes.

Memory, PCIe and cooling

DDR5-4800 ECC RDIMM in 6 channels feeds 8 small cores for gateway work. Capacity scales with large DIMMs for storage nodes. ECC stays enabled for uptime. Validated kits at rated speed are required.

PCIe Gen5 gives 96 lanes in single socket plus CXL for networking and NVMe. An 8-core node typically wires NICs plus NVMe arrays with lanes to spare. Cooling needs an SP6 server sink for 90 W with compact airflow.

Upgrade paths

On single socket SP6 the upward moves are 16-core and higher Siena parts where vCPU counts grow, without adding sockets. Memory growth to 6 channels and networking additions often help more than cores. The 8-core point already covers gateway duty at minimal power.

Outside Siena, Genoa on SP5 adds channels and sockets for larger fabrics. Most 8024P owners expand storage and IO on SP6 first, since 8 efficient cores already handle entry nodes.