AMD EPYC 8325P socket: SP6

What the AMD EPYC 8325P is

The AMD EPYC 8325P is the 32-core balanced model of the EPYC 8005 Sorano family on Socket SP6. It runs 64 threads at 2.7 GHz base with boost to 4.5 GHz, backed by 256 MB of L3 cache and a 175 W default TDP. AMD announced Sorano in February 2026 and launched the stack in May 2026, building it on full Zen 5 cores with a 5nm process instead of the denser Zen 4c cores used in Siena.

Thirty-two cores at a 2.7 GHz base suit virtualization clusters that pay per core for software licenses, plus caching storage heads and branch infrastructure hosts. The 256 MB L3 pool matches the larger 48-core and 64-core models, which gives each thread generous cache for database and image serving work. At 175 W the part sits in the middle of the SP6 power band, so standard edge chassis and airflow profiles cover it with the vendor heatsink kit.

Against the 48-core 8435P above it, the 8325P trims 16 cores for lower license counts and 25 W less draw while keeping the same 256 MB cache. Against the 24-core 8225P below it, it adds 8 cores and doubles the L3 for denser tenant mixes. No AMD 1Ku price is published on AMD pages for this model, so builders price it from board vendor quotes. The 8325P is the cache-rich pick for per-core licensed hosts.

Socket and motherboard compatibility

The 8325P fits Socket SP6, a 4,844-contact land grid array that AMD built for EPYC 8004 Siena processors from 8 to 64 cores and EPYC 8005 Sorano processors from 8 to 84 cores. Every board is single-socket only, so one 8325P fills the socket and there is no second-socket upgrade to plan. SP6 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

Sorano is a drop-in replacement on Siena boards after a BIOS update from the board maker, at the same power class. The 8325P at 175 W sits comfortably inside the Siena envelope, which keeps the swap simple on boards the vendor lists for Sorano. Memory on a converted board may stay at the Siena qualified speed rather than reaching DDR5-6400, so the vendor memory list governs the exact result. Moving from any other socket is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP6 socket feeds 6 DDR5 channels with ECC RDIMM modules, and AMD rates Sorano to 6400 MT/s for up to 3 TB per socket. Six channels at these rates keep 64 threads supplied in licensed virtualization and caching mixes. Population order, maximum capacity and per-board speed caps vary, so the vendor memory list governs every build. Where a converted Siena board caps speeds lower, cache-friendly tenants on the large 256 MB L3 feel the limit least.

PCI Express connectivity is Gen 5 with x96 lanes per socket, plus x8 Gen 3 lanes that carry board devices and slower slots. That lane budget feeds NVMe shelves, high-speed networking and timing cards on a single-socket edge board without lane sharing pressure. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to an expansion layout. CXL 2.0 memory expansion is part of the Sorano platform where the board wires it.

Cooling follows the board vendor list rather than a retail box. SP6 uses server retention with heatsinks validated per TDP class, and the 8325P at 175 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 8325P is the 48-core 8435P or the 64-core 8535P, staying on SP6 boards with attention to their higher TDP classes. The path down is the 24-core 8225P or the 16-core 8125P where clock speed or smaller power envelopes matter more than thread count. Licensed hosts can step per node without touching rack layout. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP8 is a different platform with 8 memory channels, PCIe 6.0 and higher power classes, aimed at mainstream enterprise racks rather than compact edge nodes. That change replaces board, memory population and cooling design from scratch. Buyers coming from older tower or embedded servers face the same full-platform refresh. The decision turns on whether the workload fits a small single-socket edge node or needs mainstream rack density, and the answer differs for licensed virtual farms and for central clusters.