AMD EPYC 9746 socket: SP8

What the AMD EPYC 9746 is

The AMD EPYC 9746 is the flagship standard model of the SP8 Venice stack. It runs 128 cores and 256 threads at 2.9 GHz base with boost to 4.0 GHz, backed by 512 MB of L3 cache and a 400 W default TDP. AMD launched the EPYC 9006 family in July 2026 on the TSMC 2 nm process, with SP8 as the mainstream platform. The doubled cache pool and the highest clocks of any SP8 density part mark this as the choice where memory locality decides performance.

Five hundred twelve megabytes of L3 change which problems fit on chip. Electronic design automation, computational fluid dynamics, large graph analytics and in-memory databases keep far bigger working sets resident than on the 256 MB parts, cutting trips to main memory that stall all-core runs. The 2.9 GHz base and 4.0 GHz boost also lead the dense SP8 range, so the 9746 concedes little single-thread pace while delivering full socket throughput.

At a 1Ku price of 11679 USD the 9746 is the premium SP8 standard part, above the 9736 at 10639 USD. Buyers pay for the cache and clocks directly, and the premium is justified where larger resident sets shorten job times or raise solved-model sizes. Against the 96-core 9646 it adds a third more cores plus double the cache for hosts that consolidate entire simulation queues. Power and cooling at 400 W are part of the price, since only top-rated SP8 chassis qualify.

Socket and motherboard compatibility

The 9746 fits Socket SP8, a 5572-contact land grid array covering EPYC 9006 Venice processors from 8 to 128 cores. AMD validates this standard model for single-socket and dual-socket boards, so the flagship serves both a dense 1P technical node and a 512-thread 2P host. The 400 W rating is the ceiling of the SP8 power band, which narrows board and chassis choice to designs explicitly qualified for continuous operation at that level. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P build needs two matched 9746 processors with memory populated symmetrically and cooling validated for two 400 W sockets in one chassis. A 1P build takes one processor in a chassis tuned for single-socket high-wattage airflow. There is no P suffix twin, so single-socket intent is expressed through the board. Migration from SP5 Turin or SP6 Siena hardware is a full platform replacement of board, memory and cooling.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. The 512 MB L3 pool works as a bandwidth amplifier in front of those channels, absorbing reuse that would otherwise saturate memory on dense all-core runs. MRDIMM population suits the most bandwidth-hungry codes where boards support it.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which carries accelerator fabrics, NVMe shelves and fast networking on technical computing nodes. Bifurcation and slot priority live in board firmware, so GPU host and storage layouts confirm the lane map before ordering. Gen 6 throughput per lane matters for checkpointing and dataset staging, where large jobs move gigabytes between storage, memory and accelerators continuously.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9746 at 400 W needs the highest-rated heatsink, fan policy and inlet specification the vendor offers for SP8. No cooler ships with the processor. Facilities planning for this part confirm power delivery per rack and keep sustained all-core thermals inside the vendor envelope before committing job queues to it.

Upgrade paths

On the same socket, the path down from the 9746 is the 128-core 9736 where the 512 MB cache is not needed, or the 96-core 9646 where thread count can shrink with the power bill, all staying on SP8 with the same memory and lane layout. There is no path up inside standard SP8, since this is the flagship of the mainstream stack. Each step down keeps board and memory investments where the TDP class allows, with cooling requirements easing accordingly.

A move to SP7 is a different platform with 16 memory channels, higher power classes and core counts to 256 per socket for flagship cloud and HPC installations. That change replaces board, memory population and cooling from scratch. Buyers on SP5 Turin face the same full refresh. The 9746 is the answer when the workload wants maximum cache and clocks per SP8 socket without leaving the mainstream platform.