AMD EPYC 9736 socket: SP8

What the AMD EPYC 9736 is

The AMD EPYC 9736 is the 128-core density leader of the standard SP8 Venice stack. It runs 256 threads at 2.7 GHz base with boost to 3.7 GHz, backed by 256 MB of L3 cache and a 360 W default TDP. AMD launched the EPYC 9006 family in July 2026 on the TSMC 2 nm process, with SP8 as the mainstream platform and SP7 above it for the largest nodes. On SP8 this is as many threads as one socket offers outside the cache-enlarged 9746.

One hundred twenty-eight cores per socket suit cloud-native fleets, container platforms and virtualization estates that price work by the thread. Fewer sockets per cluster means fewer boards, fewer memory populations and fewer licenses tied to sockets rather than cores. The 2.7 GHz base clock reflects the density bargain directly, trading single-thread pace for aggregate throughput that scales across hundreds of parallel tasks.

At a 1Ku price of 10639 USD the 9736 is the premium standard SP8 part below the 512 MB cache 9746. Against the 96-core 9646 it adds a third more cores for roughly a fifth more TDP, which pays off wherever hosts run at high load. Against the 64-core 9536 it nearly doubles thread count for hosts that consolidate whole racks of older servers. Buyers chasing clocks rather than count look at the frequency tuned F parts instead.

Socket and motherboard compatibility

The 9736 fits Socket SP8, a 5572-contact land grid array covering EPYC 9006 Venice processors from 8 to 128 cores. AMD validates this standard model for single-socket and dual-socket boards, so the densest SP8 silicon serves both a compact 1P node and a 512-thread 2P host. Board vendors qualify memory lists, heatsink kits and firmware per TDP class, and the 360 W rating narrows chassis choice to designs built for sustained high-wattage operation. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P build needs two matched 9736 processors with memory populated symmetrically across both sockets. A 1P build takes one processor, often in a chassis tuned for single-socket airflow and power delivery. Buyers certain they will never add a socket can take the 9736P instead and keep the price difference. Any migration from SP5 Turin or SP6 Siena hardware is a full platform replacement of board, memory and cooling.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. Behind 128 cores the per-core bandwidth is leaner than on smaller SP8 parts, so memory-bound codes prefer MRDIMM population where the board supports it. Capacity ceilings and population order come from the board vendor list.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which matters more as core count climbs because dense nodes concentrate more NVMe, networking and accelerators per socket. Bifurcation and slot priority live in board firmware, so architects confirm the lane map before committing to storage-dense layouts. Gen 6 throughput per lane keeps I/O from throttling hosts that already saturate their compute.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9736 at 360 W sits near the top of the SP8 range, demanding a heatsink and chassis airflow rated for continuous operation at that level. No cooler ships with the processor. Power capping in firmware can trim draw where the facility demands it, at some cost in sustained all-core clocks.

Upgrade paths

On the same socket, the path up from the 9736 is the 128-core 9746, which doubles L3 to 512 MB for cache-sensitive HPC and analytics codes while staying on SP8. The path down is the 96-core 9646 or 64-core 9536 where power budget or price per socket matters more than peak thread count. Single-socket sites can move sideways to the 9736P without changing capability. Each step keeps board and memory investments where the TDP class allows, with attention to the 360 W cooling requirement on the way down as well as up.

A move to SP7 is a different platform with 16 memory channels and higher power classes for flagship cloud and HPC nodes reaching 256 cores per socket. That change replaces board, memory population and cooling from scratch. Buyers on SP5 Turin face the same full refresh. The 9736 is the answer when the goal is maximum threads per SP8 socket without leaving the mainstream platform.