AMD EPYC 9476F socket: SP8

What the AMD EPYC 9476F is

The AMD EPYC 9476F is the 48-core frequency tuned model of the EPYC 9006 Venice stack on Socket SP8. It runs 96 threads at 3.65 GHz base with boost to 5 GHz, backed by 192 MB of L3 cache and a 330 W default TDP. AMD launched the EPYC 9006 family in July 2026 at its Advancing AI event, built on the TSMC 2 nm process, and positioned SP8 as the mainstream enterprise platform next to the larger SP7.

Forty-eight cores at these clocks suit cloud slices, virtual desktop brokers and application tiers where density and per-thread speed must rise together. The 3.65 GHz base is high for this core count, which keeps all-core phases moving while the 5 GHz boost answers interactive and transaction peaks. The 192 MB L3 pool spreads 4 MB per core, matching mixed enterprise working sets that cycle between cache and memory.

Against the standard 48-core 9456, the 9476F adds 0.45 GHz of base and 1.3 GHz of boost for an extra 65 W and a 1Ku price of 6695 USD against 5252 USD. Against the 32-core 9376F, the 9476F adds sixteen cores with the same boost for parallel growth. Buyers who sell response time favor the F bin, while buyers who sell capacity per watt look at the standard bin.

Socket and motherboard compatibility

The 9476F fits SP8, a 5572-contact land grid array that AMD built for EPYC 9006 Venice processors from 8 to 128 cores. Boards come in single-socket and dual-socket layouts, and AMD validates this F model for both, so the same SKU serves a 1P performance node and a 2P rack host. SP8 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P configuration needs two matched 9476F processors and a board wired for dual-socket operation, with both sockets populated to memory rules the vendor publishes. The 330 W class narrows chassis choice to designs rated for sustained high power. Moving from an older SP6 or SP5 system is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the 9476F platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. For 96 threads this bandwidth keeps cloud and virtual desktop mixes supplied when channels are filled evenly. Population order, maximum capacity and MRDIMM support vary by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which carries NVMe arrays, high speed networking and accelerators without the lane sharing compromises of smaller platforms. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. The Gen 6 signaling shortens transfer times for hosts that replicate images and session state between nodes.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9476F at 330 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a chassis or power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9476F is the 64-core 9576F for more threads at the same boost or the 64-core 9536 for density at lower power, both staying on SP8 boards with attention to their 400 W and 300 W classes. The path down is the 48-core 9456 for efficiency or the 32-core 9376F where budgets favor fewer cores. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP7 is a different platform with 16 memory channels and higher power classes, aimed at the largest cloud and HPC nodes rather than mainstream enterprise racks. That change replaces board, memory population and cooling design from scratch. Buyers coming from SP5 Turin systems face the same full-platform refresh. The decision turns on whether the workload needs SP8 balance per node or SP7 scale per socket, and the answer differs for hosted desktop pools and for large batch clusters.