AMD EPYC 7551 socket: SP3
The AMD EPYC 7551 uses the SP3 socket on server boards. It is a 32 core Naples chip at 180 W with boost to 3.0 GHz.
AMD EPYC 7551 specifications
| Cores | 32 |
|---|---|
| Threads | 64 |
| Core architecture | Zen (Naples) |
| Clocks | 2.0 GHz base, up to 3.0 GHz boost |
| Cache | 64 MB L3 |
| Processor base power (TDP) | 180 W |
| Manufacturing process | 14 nm |
| Memory support | DDR4-2666, eight channels, up to 2 TB |
| PCI Express | PCIe 3.0, 128 lanes from the CPU |
| Integrated graphics | None |
| Multiplier | Locked |
| ECC memory | Yes |
| Package | SP3 (LGA-4094) |
Motherboard compatibility
AMD EPYC 7551 needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7551 is
The EPYC 7551 is a thirty two core, sixty four thread server processor from Naples. It launched on June 20, 2017 with a 2.0 GHz base and up to 3.0 GHz boost at 180 W. Thirty two cores with full memory channels cover virtual farms and storage heads where I/O breadth matters.
Sixty four megabytes of L3 cache help many tenants share a socket without thrashing. The 180 W envelope against the 170 W 7501 gives headroom for sustained all core pace. Four Zeppelin dies with eight cores each define the package.
No graphics ship on the chip, so display duties stay with board management controllers. ECC DDR4 is mandatory in this class for error cover. The locked multiplier keeps fleets uniform.
AMD placed the 7551 as a mainstream 32 core above the 7501 and below the faster 7601. Single socket P variants later trimmed board cost for right sized nodes, while this non P part runs in one or two socket designs.
Socket and motherboard compatibility
The 7551 fits SP3 on server boards with Naples firmware. Check the vendor CPU list for board revision, since early boards need updates for later steppings. Dual socket use scales a rack to 64 cores per 2U node.
Eight DDR4 channels and 128 PCIe lanes per CPU shape board choice toward I/O rich designs. Heatsink choice follows the 180 W class with directed airflow. The Socket vs chipset: what decides whether a CPU works guide explains server socket matching.
The 32 core AMD EPYC 7501 is the lower power sibling on the same boards. The single socket 7551P variant is the cost saver where one socket suffices.
Memory, PCIe and cooling
DDR4-2666 ECC in eight channels up to 2 TB per socket is the memory target. Two DIMMs per channel is the density path, with pace guidance per board manual. RDIMM and LRDIMM types both appear in support lists.
PCIe 3.0 lanes total 128 per CPU for NICs, HBAs and NVMe drawers. Networking heavy nodes use lanes for 25 GbE and 100 GbE cards. Storage nodes split lanes across NVMe bays.
Cooling uses SP3 carrier mounting with vendor 180 W heatsinks. Paste patterns follow multi die guidance in manuals. Chassis airflow from front to back matters more than heatsink brand.
Upgrade paths
On SP3 the step is the 7601 for higher base and boost, reusing board and DDR4. Rome to Milan board updates extended some SP3 platforms further where makers released firmware.
Beyond SP3 the move is SP5 with DDR5, which needs new boards and memory. Most fleets add drives or NICs before CPU swaps. The 7551 remains a balanced 32 core for DDR4 era racks.
Frequently asked questions
What socket does the EPYC 7551 use?
It uses SP3 on server boards with Naples support.
How many cores does the 7551 have?
Thirty two cores with sixty four threads at 2.0 GHz base with up to 3.0 GHz boost.
What memory does the 7551 support?
DDR4-2666 ECC in eight channels up to 2 TB.
How many PCIe lanes does the 7551 have?
128 PCIe 3.0 lanes from the CPU.
When did the 7551 launch?
June 20, 2017 with the Naples lineup.
Sources and verification
Facts last checked against these sources on . Page last edited on .