AMD EPYC 7351P socket: SP3
The AMD EPYC 7351P uses the SP3 socket on server boards. It is a 16 core Naples chip for single socket racks at a discount to its dual socket twin.
AMD EPYC 7351P specifications
| Cores | 16 |
|---|---|
| Threads | 32 |
| Core architecture | Zen (Naples) |
| Clocks | 2.4 GHz base, up to 2.9 GHz boost |
| Cache | 64 MB L3 and 8 MB L2 (72 MB total) |
| Processor base power (TDP) | 170 W (155 W with DDR4-2400) |
| Manufacturing process | 14 nm |
| Memory support | DDR4-2666, eight channels, up to 2 TB |
| PCI Express | PCIe 3.0, 128 lanes from the CPU |
| Integrated graphics | None |
| Multiplier | Locked |
| ECC memory | Yes |
| Package | SP3 (LGA-4094) |
Motherboard compatibility
AMD EPYC 7351P needs a motherboard with a SP3 socket. Chipset by chipset data for this codename is not recorded yet. See the SP3 chipset list and the board maker's CPU support list.
SP3 at a glance
| Type | LGA, 4,094 contacts |
|---|---|
| Package size | 58.5 × 75.4 mm |
| Introduced | June 2017 |
| Memory | DDR4 ECC RDIMM, 8 channels to DDR4-3200, up to 4 TB per socket |
| Cooler mounting holes | Board specific (server heatsink) |
What the EPYC 7351P is
The EPYC 7351P is a sixteen core, thirty two thread server processor with a 2.4 GHz base and up to 2.9 GHz boost. It carries 8 MB of L2 with 64 MB of shared L3 and a 170 W TDP on the 14 nm process. AMD launched it on June 20, 2017 with the EPYC 7001 family.
The P suffix marks single socket only silicon at a large discount to the dual socket 7351. Reviews measured the same clocks with dual socket hardware disabled. The 170 W rating pairs with DDR4-2666, dropping to 155 W with DDR4-2400.
There is no integrated graphics. ECC memory with RDIMM and LRDIMM support is standard. Pricing is omitted here because launch lists disagree. The multiplier is locked, against unlocked flags in one database that do not apply to servers.
Socket and motherboard compatibility
The 7351P fits SP3 on single socket server boards. Dual socket boards reject P parts, since the second socket hardware is disabled. Check the board vendor list for the exact P SKU before ordering.
Server boards carry eight channel DDR4 and 128 PCIe 3.0 lanes per CPU for NVMe, network and accelerators. Rack chassis need front to back airflow with vendor qualified SP3 heatsinks. The Socket vs chipset: what decides whether a CPU works guide covers platform support.
The chip ships tray only with no cooler. The EPYC 7351 is the dual socket twin on the same boards where two sockets matter.
Memory, PCIe and cooling
Memory support is DDR4-2666 in eight channels up to 2 TB, with ECC and RDIMM or LRDIMM modules. Dropping to DDR4-2400 drops the TDP to 155 W with some bandwidth. Sixteen DIMMs per socket hold rated speed most easily.
PCI Express arrives as version 3.0 with 128 lanes from the CPU, the same count in one socket designs. NICs and NVMe arrays share the huge lane budget of a single socket rack. Cooling uses vendor 170 W server heatsinks with directed airflow.
Upgrade paths
On the same socket the step up is a higher core P part such as the EPYC 7401P where thread density matters, keeping board and DDR4. The 7351P keeps its place where sixteen cores cover the rack at single socket pricing.
Moving past SP3 means a new board on a current server platform. Rack owners usually add memory or network cards before replacing processors.
Frequently asked questions
What socket does the EPYC 7351P use?
It uses SP3 on single socket server boards. Dual socket boards reject P parts.
How many cores does the 7351P have?
Sixteen cores with multithreading give thirty two threads at 2.4 GHz base with up to 2.9 GHz boost, at 170 W.
What does the P suffix mean?
Single socket only with dual socket hardware disabled, at a large discount to the dual socket twin. Clocks match the 7351.
What memory does the 7351P support?
DDR4-2666 in eight channels up to 2 TB, with ECC and RDIMM or LRDIMM modules. DDR4-2400 drops the TDP to 155 W.
How many PCIe lanes does the 7351P have?
128 PCIe 3.0 lanes from the CPU, the same count as dual socket designs, for NICs and NVMe arrays.
Sources and verification
Facts last checked against these sources on . Page last edited on .