AMD Athlon XP 3000+ (333FSB) socket: Socket 462
The AMD Athlon XP 3000+ (333FSB) uses the Socket 462 socket. It is a 74.3 W single-core Barton desktop part at 2167 MHz with 512 KB of L2 cache for Socket 462 DDR boards with a 333 MT/s bus.
- Socket
- Socket 462
- Launched
- February 2003
- Cores and threads
- 1 and 1
- Default TDP
- 74.3 W
- Codename
- Barton
- Segment
- Desktop
- Family
- AMD Athlon XP
- Clocks
- 2.17 GHz
AMD Athlon XP 3000+ (333FSB) specifications
| Cores | 1 |
|---|---|
| Threads | 1 |
| Core architecture | Barton cores on 130 nm |
| Clocks | 2167 MHz (no turbo) |
| Cache | 512 KB L2 |
| Default TDP | 74.3 W |
| Manufacturing process | 130 nm |
| Memory support | DDR through the board chipset |
| Front side bus | 333 MT/s |
| PCI Express | AGP or PCI from the board chipset |
| Integrated graphics | None (board graphics where fitted) |
| Multiplier | Locked (13x) |
| Package | Socket 462 (462-pin OPGA) |
Motherboard compatibility
AMD Athlon XP 3000+ (333FSB) needs a motherboard with a Socket 462 socket. Chipset by chipset data for this codename is not recorded yet. See the Socket 462 chipset list and the board maker's CPU support list.
Socket 462 at a glance
| Type | PGA, 462 contacts |
|---|---|
| Package size | 49.53 × 49.53 mm |
| Introduced | June 2000 |
| Memory | DDR through the board chipset, single channel |
| Cooler mounting holes | Socket lug (clip) |
What the Athlon XP 3000+ (333FSB) is
The AMD Athlon XP 3000+ (333FSB) is a 2167 MHz single-core desktop processor from February 2003. It runs one K7 Barton core at 2167 MHz with no turbo, so 1 core gives 1 thread. Cache is 512 KB of L2 on a 130 nm process. Power is rated at 74.3 W in a Socket 462 package with part number AXDA3000DKV4D on a 333 MT/s front side bus with a 13x multiplier at 1.65 V. The cpu_list 68 W value differs from the table 74.3 W, and the table value is used here.
The 333FSB version predates the 400FSB 3000+ at 2100 MHz from May 2003, trading a faster bus for 67 MHz more clocks at higher power. Both share the 3000+ rating with 512 KB, so bus and power separate the bins. AMD placed the 333FSB version in February 2003 with the 2800+ and 2500+ Barton parts. The chip supports MMX, Extended MMX, SSE, 3DNow and Enhanced 3DNow. Suffixes are part of the model here, giving each bus its own slug.
Higher power with a slower bus marks the older bin. The 74.3 W rating against 68.3 W on the 400FSB sibling reflects early stepping current at higher clocks. That is why the 333FSB version needs a stronger heatsink despite sharing the rating.
Socket and motherboard compatibility
The 3000+ (333FSB) fits Socket 462 DDR boards with a 333 MT/s bus and Barton support. It needs 333 MT/s chipset paths. The Socket vs chipset: what decides whether a CPU works guide covers pairing rules.
Mainstream DDR towers are the natural match. Boards listing the 333FSB 3000+ accept the chip with a 74.3 W cooler. The 400FSB sibling needs 400 MT/s paths instead.
Memory, PCIe and cooling
Memory is DDR through the board chipset, matched to the 333 MT/s bus. The CPU has no controller.
A 333 MT/s bus ties the CPU to the chipset, while AGP and PCI hang off the chipset. No PCIe lanes originate on the die. Cooling uses the socket lug clip with a 74.3 W heatsink.
Upgrade paths
On Socket 462 the steps are Barton 3200+ parts with the same cache on faster buses. The 400FSB 3000+ offers the same rating with a faster bus at lower power. Beyond Socket 462 a move to Socket 754 needs a new board. The chip lifts with the lever, so swaps need no solder work.
Frequently asked questions
What socket does the Athlon XP 3000+ (333FSB) use?
Socket 462, on DDR boards with a 333 MT/s bus and Barton support.
How many cores does the Athlon XP 3000+ (333FSB) have?
One core and 1 thread at 2167 MHz with 512 KB of L2 cache.
What memory works with the Athlon XP 3000+ (333FSB)?
DDR through the board chipset, matched to the 333 MT/s bus.
Can the Athlon XP 3000+ (333FSB) be upgraded?
Barton 3200+ parts share the socket. The 400FSB sibling offers a faster bus at lower power.
Sources and verification
Facts last checked against these sources on . Page last edited on .