AMD EPYC 9376F socket: SP8

What the AMD EPYC 9376F is

The AMD EPYC 9376F is the 32-core frequency tuned model of the EPYC 9006 Venice stack on Socket SP8. It runs 64 threads at 3.8 GHz base with boost to 5 GHz, backed by 192 MB of L3 cache and a 285 W default TDP. AMD launched the EPYC 9006 family in July 2026 at its Advancing AI event, built on the TSMC 2 nm process, and positioned SP8 as the mainstream enterprise platform next to the larger SP7.

Thirty-two cores at 3.8 GHz base suit application servers, mid-size virtual clusters and software build tiers where both core count and per-thread speed matter. The 192 MB L3 pool spreads 6 MB per core, which steadies multi-tenant performance when many processes contend for data. At 285 W the part sits above the standard 250 W tier, trading power for a higher sustained floor and a higher peak.

Against the standard 32-core 9356, the 9376F adds 0.2 GHz of base and 0.5 GHz of boost for an extra 35 W and a 1Ku price of 4849 USD against 3789 USD. Against the 24-core 9276F, the 9376F adds eight cores and doubles the cache for parallel mixes that have outgrown smaller bins. Buyers who measure response time under load favor the F bin, while buyers who optimize for cost per virtual machine look at the standard bin.

Socket and motherboard compatibility

The 9376F fits SP8, a 5572-contact land grid array that AMD built for EPYC 9006 Venice processors from 8 to 128 cores. Boards come in single-socket and dual-socket layouts, and AMD validates this F model for both, so the same SKU serves a 1P performance node and a 2P rack host. SP8 boards are platform designs rather than desktop chipsets, so memory lists, heatsink kits and firmware all come from the board vendor. See Socket vs chipset: what decides whether a CPU works for how socket, platform and firmware fit together on server boards.

A 2P configuration needs two matched 9376F processors and a board wired for dual-socket operation, with both sockets populated to memory rules the vendor publishes. A 1P board takes one 9376F and suits latency sensitive application hosts. Moving from an older SP6 or SP5 system is a full platform change with board, memory and heatsinks replaced together.

Memory, PCIe and cooling

Each SP8 socket feeds 8 DDR5 channels with two DIMMs per channel, using RDIMM, 3DS RDIMM or MRDIMM modules. AMD rates the 9376F platform to 8000 MT/s with RDIMM and 12800 MT/s with MRDIMM, giving up to 512 GB/s per socket with RDIMM and 819.2 GB/s with MRDIMM. Eight channels at these rates keep 64 threads supplied in compilation and virtualization mixes. Population order, maximum capacity and MRDIMM support vary by board, so the vendor memory list governs every build.

PCI Express connectivity is Gen 6 with x128 lanes per socket, which carries NVMe arrays, high speed networking and accelerators without the lane sharing compromises of smaller platforms. Lane bifurcation and CXL behavior follow board firmware, so architects confirm slot maps before committing to a storage-heavy layout. The Gen 6 links help hosts that move container images and backup streams at high rates.

Cooling follows the board vendor list rather than a retail box. SP8 uses server retention with heatsinks validated per TDP class, and the 9376F at 285 W needs a heatsink kit rated for that class in the intended chassis airflow. No cooler ships with the processor. Firmware power limits can cap draw below the default where a chassis or power budget demands it, at some cost in sustained clocks.

Upgrade paths

On the same socket, the path up from the 9376F is the 48-core 9476F for more threads at the same boost or the 48-core 9456 for density at lower clocks, both staying on SP8 boards with attention to their TDP classes. The path down is the 32-core 9356 for efficiency or the 24-core 9276F where budgets favor fewer cores. Each of these moves keeps board, memory and heatsink investments where the TDP class allows.

A move to SP7 is a different platform with 16 memory channels and higher power classes, aimed at the largest cloud and HPC nodes rather than mainstream enterprise racks. That change replaces board, memory population and cooling design from scratch. Buyers coming from SP5 Turin systems face the same full-platform refresh. The decision turns on whether the workload needs SP8 balance per node or SP7 scale per socket, and the answer differs for application tiers and for dense compute pools.