Intel Xeon 6503P socket: LGA 4710
The Intel Xeon 6503P uses the LGA 4710 socket. It is an 8 core Granite Rapids server processor for single and dual socket boards with DDR5 memory and PCI Express 5.0.
- Socket
- LGA 4710
- Launched
- May 2026
- Cores and threads
- 8 and 16
- Base power
- 135 W
- Codename
- Granite Rapids
- Segment
- Server
- Family
- Intel Xeon
- Clocks
- 2.8 / 4.3 GHz
Intel Xeon 6503P specifications
| Cores | 8 |
|---|---|
| Threads | 16 (with Hyper-Threading) |
| Clocks | 2.8 GHz base, up to 4.3 GHz boost (3.8 GHz all-core) |
| Cache | 48 MB |
| Processor base power (TDP) | 135 W |
| Manufacturing process | Intel 3 |
| Memory support | DDR5 up to 6400 MT/s, 8 channels, up to 4 TB |
| PCI Express | PCIe 5.0, up to 88 lanes |
| Integrated graphics | None |
| ECC memory | Yes |
| Package | FCLGA4710 (77.5 × 56.5 mm) |
| Scalability | 2S (up to 2 sockets) |
| Launch price | $676 (Intel RCP at launch) |
Motherboard compatibility
Intel Xeon 6503P needs a motherboard with a LGA 4710 socket. Chipset by chipset data for this codename is not recorded yet. See the LGA 4710 chipset list and the board maker's CPU support list.
LGA 4710 at a glance
| Type | LGA, 4,710 contacts |
|---|---|
| Package size | n/a |
| Introduced | June 2024 |
| Memory | DDR5, 8 channels |
| Cooler mounting holes | Board specific (server heatsink) |
What the Xeon 6503P is
The Xeon 6503P is an 8 core server processor from the Xeon 6 family under the codename Granite Rapids. It carries 8 Performance-cores for 8 cores and, with Hyper-Threading, 16 threads. The base frequency is 2.8 GHz with maximum turbo to 4.3 GHz and all core turbo to 3.8 GHz. The last level cache totals 48 MB. Intel builds the part for cloud, enterprise, and edge servers that need a low core count with high per core speed.
Intel rates the thermal design power at 135 W. The part uses Intel 3. Memory support covers DDR5 up to 6400 MT/s in 8 channels up to 4 TB with ECC. Expansion provides PCI Express 5.0 with up to 88 lanes. Scalability covers 2S, so up to two sockets can work together with 24 GT/s UPI across 3 links.
The processor launched in the second quarter of 2026 at 676 dollars Intel recommended customer price. It sits at the entry of the 6500P line for single and dual socket boards where socket count and memory capacity matter more than core count. There is no integrated graphics, so display or compute acceleration needs a discrete device. The package uses FCLGA4710 with carrier E2B and measures 77.5 × 56.5 mm.
Socket and motherboard compatibility
The Xeon 6503P fits the LGA 4710 socket. The land grid array has 4,710 contacts and supports Sierra Forest and Granite Rapids parts on mainstream single and dual socket server boards. Compatibility follows the board vendor CPU support list for each model.
The socket file lists no desktop chipset groups, so there is no retail chipset pick. Board firmware, memory population rules, and power limits come from the server vendor. Buyers should confirm the 6503P on the vendor list with the planned BIOS revision before ordering.
Heatsink choice follows the board vendor list for 135 W parts. The CPU cooler compatibility by socket explains why server sockets use board specific heatsinks rather than retail mounting patterns. Air and liquid options are qualified per chassis and airflow direction.
Memory, PCIe and cooling
The memory controller supports DDR5 up to 6400 MT/s with 8 channels and up to 4 TB per socket. ECC is supported. RDIMM and 3DS RDIMM types fit the enterprise use case, and final speed follows DIMM population per channel. Two DIMMs per channel lower the rate, so vendors publish tested layouts for full capacity.
For I/O the chip provides PCI Express 5.0 with up to 88 lanes for network, storage, and accelerators. UPI links at 24 GT/s connect two sockets in a 2S layout. The platform also carries DMI 4.0 to the board controller for management and onboard devices.
Power and cooling center on 135 W with 78 degrees C maximum case temperature and 97 degrees C maximum junction from the digital sensor. There is no boxed cooler. System integrators size heatsinks and fans for continuous load at the inlet temperature of each rack, and firmware sets sustained and burst limits.
Upgrade paths
Within LGA 4710 the path up is a higher core Granite Rapids part on the same board where power and memory allow. A move from 8 cores to 16 or 32 cores keeps the socket while changing thermal and license cost. The vendor list shows which higher parts the board and BIOS revision accept.
A platform change to another socket needs a new board and new memory population. Socket, heatsink, and firmware stay with the old system. Buyers moving from a desktop socket such as LGA 1851 should plan for server chassis, redundant power, and ECC RDIMM memory rather than desktop DIMMs.
For entry servers that stay at 8 cores the 6503P can remain in place while storage and network grow. Adding drives, network cards, or accelerators uses the 88 PCIe 5.0 lanes before a CPU change is needed. When thread count limits the workload, a same socket part with more cores is the next step.
Frequently asked questions
What socket does the Intel Xeon 6503P use?
The Intel Xeon 6503P uses LGA 4710. It fits mainstream single and dual socket server boards for Sierra Forest and Granite Rapids parts. Always confirm the part on the board vendor CPU support list.
What memory does the Xeon 6503P support?
DDR5 up to 6400 MT/s in 8 channels up to 4 TB with ECC. Final speed follows the DIMM type and population per channel, so check the vendor memory guide for the planned capacity.
How many PCIe lanes does the Xeon 6503P provide?
Up to 88 lanes of PCI Express 5.0 for network, NVMe storage, and accelerators. UPI at 24 GT/s across 3 links connects two sockets in a 2S system.
Can two Xeon 6503P processors work together?
Yes, up to two sockets. The scalability field lists 2S. Single socket boards use one 6503P, while dual socket boards use two with matched firmware and memory.
Sources and verification
- Intel Xeon 6503P processor specifications (Intel ARK)
- Intel Xeon 6503P specs and benchmarks (Technical City)
Facts last checked against these sources on . Page last edited on .