AMD Ryzen AI Embedded X168i socket: FP11

What the Ryzen AI Embedded X168i is

The Ryzen AI Embedded X168i combines the smallest X100 CPU with industrial temperature qualification. Eight Zen 5 cores with 16 threads run 3.6 GHz base to 5.0 GHz boost, cache is 8 MB of L2 with 32 MB of L3 plus 32 MB of MALL cache, and graphics hold the full 32 RDNA 3.5 compute units to 2800 MHz with an XDNA 2 NPU of up to 50 TOPS. Default TDP is 55 W inside the 45 to 120 W range on TSMC 4 nm.

The i grade qualifies the junction from minus 40 to 105 degrees against 0 to 105 on the standard AMD Ryzen AI Embedded X168. Everything else repeats: clocks, cache, graphics size, memory support and power. That makes the X168i the graphics-weighted industrial SKU, for equipment where vision and inference outweigh thread count and the enclosure sees frost or heat.

AMD's lifecycle terms give 10-year availability with last time buy in 2037, and sampling began in June 2026 ahead of fourth quarter production. The uniform Zen 5 cores with AVX-512 keep scheduling simple for control software beside the accelerators.

Socket and board compatibility

The chip solders to its board in FP11, 2,077 balls on 37.5 × 45 mm, with no socket, no swap and no later upgrade. Board options span chip-down designs and COM-HPC or Kria AI modules, all validated for the industrial span including joint and thermal interface. Production modules were announced from congatec, Arbor, iBase, IEI, Sapphire and Seavo.

Firmware is SKU specific, so an X168i build is qualified as one. Developers start on reference boards such as Maple or the Kria AI robotics platform before committing to custom hardware.

Inside FP11 the industrial ladder runs through the AMD Ryzen AI Embedded X188i and the 16-core flagship for more threads. Outside Halo, FP8 carries smaller industrial SKUs.

Memory, PCIe and cooling

Eight channels of soldered LPDDR5X to 8533 MT/s give a 256-bit unified pool to 128 GB with Link-ECC for CPU, GPU and NPU. On an 8-core SKU the wide bus mostly serves the 32 compute units, which suits inference-heavy edge nodes. Capacity freezes at manufacture.

I/O offers 16 PCIe Gen4 lanes, two USB4 ports, USB 3.2 and 2.0, and four display outputs to 7680x4320. Lanes go to NVMe, networking and sensors per board manual, while the integrated GPU handles display and compute. Cold rated operation extends to connectors and interfaces, not only the die.

Cooling is a system heatsink or cold plate sized for the configured TDP between 45 and 120 W on the lidless package. Validation must cover continuous load at both temperature extremes with an interface material rated for the span. No boxed cooler exists.

Platform, software and lifecycle

The X168i addresses outdoor HMIs, inspection rigs, gateways and vehicles that need strong graphics and AI with modest CPU count in harsh air. Linux, ROCm, PyTorch, ONNX and TensorFlow with Xen separation form the stack, shared with the rest of the X100 series so product families reuse one software program.

The 10-year supply to 2037 protects certified designs, and the industrial grade protects the deployment. Together they explain the premium over commercial silicon with similar headline speeds.

Upgrade paths

Soldered packages cannot be upgraded. More industrial threads mean a new build around a bigger i model on FP11, and lower budgets mean FP8 P100 industrial grades. Desktop Gorgon silicon uses AM5 instead.

Memory size cannot grow after manufacture, so size the unified pool for the lifetime models at project start.